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Stefano Di Carlo

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Press Release

CLERECO: Cross Layer Early Reliability Evaluation for the Computing Continuum

FP7 EU funded research project launched to investigate design methodologies for early reliability evaluation for digital systems

The European Commission has launched a joint FP7 Collaboration Project CLERECO aiming to investigate new design methods for early reliability evaluation of digital systems in the forthcoming computing continuum. The CLERECO project consortium includes Politecnico di Torino(Italy) acting as project coordinator, National and Kapodistrian University of Athens (Greece), Centre National de la Recherche Scientifique - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier (France),Intel Corporation Iberia (Spain), Thales SA (France), Yogitech S.P.A. (Italy) and ABB AS (Norway).

Advanced multifunctional computing systems based on future technologies hold the promise of a significant increase of the computational capability that will offer end-users ever improving services and functionalities (e.g., next generation mobile devices, cloud services, etc.).

Reliability of electronic systems will become an ever-increasing challenge for information and communication technology and must be guaranteed without penalizing or slowing down the characteristics of the final products.

CLERECO research project recognizes the importance of accurately evaluating the reliability of systems early in the process to be one of the most important and challenging tasks toward this goal. Being able to precisely evaluate the reliability of a system means being able to carefully plan for specific countermeasures rather than resorting to worst-case approaches. CLERECO project will be fundamental in the development of scaled systems for the next decade..

The proposed CLERECO framework for efficient reliability evaluation and therefore efficient exploitation of reliability oriented design approaches starting with the earliest phases of the design process will enable circuit integration to continue at exponential rates. It will enable the design and manufacture of future systems for the computing continuum at a minimum cost (e.g., up to 50% less area, up to 50% less energy, etc.) contrary to existing worst-case design solutionsfor reliability.

The applications of such chips will play a major role in our society and can be seen through the prism of future computing systems ranging from avionics, automobile, smartphones, mobile systems, Personal Computers (PCs) and future servers utilized in the settings of Data Centers, Grid Computing, Cloud Computing and other types of HPC systems.

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Stefano Di Carlo received the MS degree in computer engineering and the PhD degree in information technologies from the Politecnico di Torino, Italy, where he has been an assistant professor in the Department of Control and Computer Engineering since 2008. He is a golden core member of the IEEE Computer Society and a senior member of the IEEE.